In general, a semiconductor integrated circuit includes a large number of transistors formed on a semiconductor substrate, and a wiring layer formed on an upper layer of the semiconductor substrate and connecting each transistor. Usually, a wiring pattern for connecting each transistor is determined at a design stage of a semiconductor integrated circuit, and it is impossible to change the connection between the transistors after manufacturing the semiconductor integrated circuit.
On the other hand, a programmable logic integrated circuit such as an FPGA (Field Programmable Gate Array) has a configuration in which connection of a plurality of logical operation circuits (logic blocks) provided inside can be changed even after manufacturing. Therefore, by freely combining a plurality of logic blocks, a user can form (implement) a desired logic circuit in a programmable logic integrated circuit. Information (configuration information) necessary for forming a desired logic circuit is stored in a memory element of the programmable logic integrated circuit. An SRAM (Static Random Access Memory) cell, an antifuse, a floating gate MOS (Metal Oxide Semiconductor) transistor, or the like is used as a memory element for storing configuration information.
Since switches for connecting these memory elements and logic blocks in a changeable manner are usually formed in the same layer as a logic block composed of a large number of transistors, they cause a large area overhead factor. Therefore, the chip area of the programmable logic integrated circuit is increased, and the manufacturing cost is increased. As the layout area of memory elements and switches increases, the ratio of logic blocks to the chip area decreases.
Therefore, a programmable logic integrated circuit using a variable resistance element that can be formed in a wiring layer has been proposed as a switch that can change connection between logic blocks after manufacturing while suppressing an increase in the layout area. For example, programmable logic integrated circuits described in Patent Literature 1 (PTL1), Patent Literature 2 (PTL2), and Non Patent Literature 1 (NPL1) have a configuration in which a variable resistance element made of a solid electrolyte material containing a metal ion is arranged between a first wiring layer and a second wiring layer formed on the first wiring layer. Resistance value of the variable resistance element can be changed by applying a bias voltage in the forward direction or the reverse direction across both ends of the variable resistance element, and the ratio of a high resistance state (OFF state) to a low resistance state (ON state) is 105 or more. In other words, the variable resistance element functions as a switch for electrically connecting or disconnecting the first wiring and the second wiring.
For connection and disconnection of wiring in the programmable logic integrated circuit of the background art, a switch cell having an SRAM cell as a memory element and one transistor with a switch function is used. On the other hand, since the variable resistance element has both a memory function and a switch function, a switch cell can be realized with one variable resistance element.
According to PTL1, by arranging a variable resistance element at each intersection of a first wiring group and a second wiring group crossing the first wiring group, a crossbar switch capable of connecting or disconnecting an arbitrary wiring of the first wiring group and an arbitrary wiring of the second wiring group can be realized with a compact size. As a result, it is expected that the performance of a programmable logic integrated circuit is improved by considerably reducing the chip area and improving the use efficiency of a logic block. Since an ON/OFF state of the variable resistance element is maintained even when power supply to the programmable logic integrated circuit is discontinued, there is also an advantage that it is possible to omit the trouble of loading configuration information every time the power is turned on.
By the way, it is known that, in a semiconductor integrated circuit including a programmable logic integrated circuit, it is very effective to provide a redundant circuit in preparation for defects of transistors and wirings generated during manufacturing, in order to improve production yield. For example, Patent Literature 3 (PTL3) or Patent Literature 4 (PTL4) discloses a technique in which a redundant circuit is provided, and a circuit (defective circuit) in which a failure occurs is replaced by the redundant circuit.
When a defective circuit is detected in a screening test before shipping, it is common that the shipment is made after forming a route that bypasses the defective circuit by a redundant circuit. By this, even when a defective circuit is included in a shipped programmable logic integrated circuit, a user of the programmable logic integrated circuit can configure a desired logic circuit without being conscious of the defective circuit.